Design and Performance Comparison of 16-Bit UT Multiplier using Reversible Logic
نویسندگان
چکیده
منابع مشابه
Design of 16-bit Multiplier Using Efficient Recoding Techniques
Multiplier is the major component for processing of large amount of data in DSP applications. Using different recoding schemes in Fused Add-Multiply (FAM) design for the reduction of power and look up tables. The performance of 16-bit signed and unsigned multipliers were designed and obtained results are tabulated using Efficient Modified Booth Recoding (EMBR) techniques, which can be used for ...
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ژورنال
عنوان ژورنال: International Journal for Research in Applied Science and Engineering Technology
سال: 2019
ISSN: 2321-9653
DOI: 10.22214/ijraset.2019.4161